1. Field of the Invention
This invention relates to a method for fabricating a semiconductor component, more particularly to a method for fabricating a thin film transistor substrate.
2. Description of the Related Art
Referring to FIG. 1, a thin film transistor substrate (TFT substrate), which is one of the most important elements in a liquid crystal display, includes a transparent glass substrate 11, and a plurality of pixel units 12 regularly arranged on the substrate 11. Each of the pixel units 12 includes a thin film transistor structure (TFT structure) 18, a storage capacitor (Cst) 19 spaced apart from the TFT structure IS, and a pixel electrode layer 17 electrically connecting the TFT structure 18 to the storage capacitor 19. The storage capacitor 19, based on the location thereof in the TFT substrate, can be classified as a Cs-on-gate structure or a Cs-on-common structure. In FIG. 1, the Cs-on-gate structure is used as an example for illustration.
FIG. 2 is a fragmentary cross-sectional view taken along line A-A in FIG. 1, and FIG. 3(a) or 3(b) is a fragmentary cross-sectional view taken alone line B-B in FIG. 1.
Referring to FIG. 2, the TFT structure 18 includes: a gate electrode 182 formed on the substrate 11, an insulating film 183 covering the substrate 11 and the gate electrode 182, an active semiconductor layer 184a formed on the insulating film 183, a doped semiconductor layer 184b formed on the active semiconductor layer 184a and interrupted by a channel 184e, source and drain electrodes 185a, 185b formed on the doped semiconductor layer 184b and located respectively at two opposite sides of the channel 184e, and a passivation film 186 covering the source and drain electrodes 185a, 185b. The passivation film 186 is formed with two contact holes 185c, through which the source and drain electrodes 185a, 185b are partially exposed.
The storage capacitor 19 has a metal-insulator-semiconductor (MIS) structure as shown in FIG. 3(a), or a metal-insulator-metal (MIM) structure as shown in FIG. 3(b). As shown in FIG. 3(a), the MIS structure of the storage capacitor 19 includes: a lower capacitor electrode 192 formed on the substrate 11, an insulating film 193 covering the lower capacitor electrode 192 and the substrate 11, an active semiconductor layer 194a formed on the insulating film 193, a doped semiconductor layer 194b formed on the active semiconductor layer 194a, an upper capacitor electrode 195 formed on the doped semiconductor layer 194b, and a conductive layer 196 that is formed on the upper capacitor electrode 195 and that is a portion of the pixel electrode layer 17.
As shown in FIG. 3 (b), the MIM structure of the storage capacitor 19 includes: a lower capacitor electrode 192 formed on the substrate 11, an insulating film 193 covering the lower capacitor electrode 192 and the substrate 11, and a conductive layer 196 that is formed on the insulating film 193 and that is a portion of the pixel electrode layer 17.
The pixel electrode layer 17 covers predetermined regions of the TFT structure 18 and the storage capacitor 19 so that the TFT structure 18 and the storage capacitor 19 are electrically connected to each other through the pixel electrode layer 17.
Referring to FIG. 4, a method for fabricating the TFT substrate shown in FIG. 1 involves a five-photomask process, and includes a gate electrode forming step 101, a semiconductor forming step 102, a source/drain electrode forming step 103, a contact hole forming step 104, and a pixel electrode layer forming step 105.
Referring to FIG. 5, in step 101, a metal layer 12a and a photoresist layer 200 made of a positive-type photoresist material are sequentially formed on the substrate 11, and a lithography process is conducted using a gate mask (M1) to form the first metal layer 12a into the gate electrode 182.
Referring to FIG. 6, in step 102, the insulating film 183, the active semiconductor layer 184a, the doped semiconductor layer 184b, and a photoresist layer 200 are sequentially formed on the substrate 11 to cover the gate electrode 182, and a lithography process is conducted using an active mask (M2) to form a patterned photoresist A portion of each of the doped semiconductor layer 184b, the active semiconductor layer 184a, and the insulating film 183, which is uncovered by the patterned photoresist, is removed.
Referring to FIG. 7, in step 103, an ohmic contact metal film 15 and a photoresist layer 200 are sequentially formed on the doped semiconductor layer 184b, and a lithography process is conducted using a source/drain mask (S/D mask, M3) so that the channel 184e is formed to expose the active semiconductor layer 184a at a location corresponding to the gate electrode 182, and so that the ohmic contact metal layer 15 is formed into the source and drain electrodes 185a, 185b at two opposite sides of the channel 184e. 
Referring to FIG. 8, in step 104, the passivation film 186 is formed to cover the source and drain electrodes 185a, 185b, and the exposed active semiconductor layer 184a, and a photoresist layer 200 is formed on the passivation film 186. A lithography process is conducted using a contact-hole mask (M4) so that the two contact holes 185c are formed by removing two portions of the passivation film 186 on the two opposite sides of the channel 184e to partially expose the source and drain electrodes 185a, 185b. 
Referring to FIG. 9, in step 105, a transparent conductive layer 17a is formed on the passivation film 186 and the exposed parts of the source and drain electrodes 185a, 185b. A lithography process is conducted using a pixel mask (M5) so that the transparent conductive layer 17a is patterned to form the pixel layer 17. Accordingly, the TFT structure 18 as shown in FIG. 2 is obtained.
On the other hand, the storage capacitor 19 can also be obtained while forming the TFT structure 18, and the procedures for forming the storage capacitor 19 are well-known in the relevant art. Therefore, detailed descriptions thereof are omitted herein for the sake of brevity.
In order to reduce equipment costs, four-photomask and three-photomask processes are also proposed nowadays. In such processes, a multi-tone mask, which further has a partially transparent region having a transmittance between a fully transparent region and a non-transparent region, is used to replace a normal mask (i.e., a single-tone mask only including the fully transparent region and the non-transparent region), such as the gate mask (M1), the active mask (M2), the S/D mask (M3), the contact-hole mask (M4) or the pixel mask (M5). For example, in the four-photomask process, a multi-tone mask is used to replace the active mask (M2) and the S/D mask (M3) when conducting steps 102 and 103. In the three-photomask process, two multi-tone masks are used, one of which is used to replace the active mask (M2) and the S/D mask (M3) when conducting steps 102 and 103, and the other of which is used to replace the contact-hole mask (M4) and the pixel mask (M5) when simultaneously conducting steps 104 and 105.
In current four-photomask or three-photomask processes, the multi-tone mask, aside from the fully transparent region and the non-transparent region, has only one partially transparent region, and is used to replace the single-tone mask. By reducing the numbers of the photomasks and fabricating the TFT substrate using the above-mentioned multi-tone mask (s), an object of cost reduction can be achieved.
Referring to FIG. 10, when a multi-tone mask is used to replace the contact-hole mask (M4) and the pixel mask (M5) in the three-photomask process, the transparent conductive layer 17a is formed on the passivation film 186, the exposed parts of the source and drain electrodes 185a, 185b, and a remaining portion of the photoresist layer 200 that is formed on a portion of the passivation film 186 and between the two contact holes 185c. Thereafter, the pixel electrode layer 17 is formed by removing the remaining portion of the photoresist layer 200 and a part of the transparent conductive layer 17a on the remaining portion of the photoresist layer 200 using a lift-off method. However, the removal of the part of the transparent conductive layer 17a and the photoresist layer 200 using the lift-off method may adversely affect yield of the TFT substrate. Besides, the transparent conductive layer 17a is Insoluble in a photoresist-stripping agent, and thus, a filter used in a device for recycling and supplying the photoresist-stripping agent is likely to be clogged with the removed transparent conductive layer 17a, thereby reducing service life thereof.